Our new Digital ADC technology can be implemented in a digital only silicon technology without using any of the analog IP blocks traditionally used for ADC designs. This reduces the design cycle time and cost of integrating ADCs in to ASICs, and can be implemented in fully digital microchips such as FPGAs avoiding the use of external costly ADCs and saving board space.
Configurations are available that support up to 14 bits of resolution at 10 kHz bandwidth, 12 bits up to 20 kHz bandwidth, and 10 bits up to 100 kHz bandwidth. Development is continuing to support higher bandwidths.
Block Diagram of the Digital ADC
The analog input is optionally AC-coupled to adjust the DC bias, and then enters the FPGA or ASIC on the non-inverting input of an LVDS input buffer, where it is compared to the reconstructed feedback signal on the inverting input. The difference signal is processed by the digital logic to generate the feedback signal and the ADC output samples that can be used by the rest of the FPGA or ASIC.
The only other signal required by the Digital ADC is a clock input. The frequency of the clock and the characteristics of the tracking loop affect the bandwidth and signal-to-noise ratio of the Digital ADC.
Digital Sigma-Delta DAC Family
Stellamar offers a family of Sigma-Delta DACs. These digital DACs can be implemented in digital only silicon technologies such as FPGAs or Digital ASICs.
Within this family, a DAC can be quickly built and customized for your application.
- Up to 16 bit resolution
- Up to 100 kHz bandwidth
The benefits of this new technology compared with similar performance traditional include:
- No analog block development required
- Shorter / lower risk design cycles
- Process / technology independent
- Digital layout
- Smaller silicon area
- Lower power consumption
- Suitable for applications requiring very low supply voltage
- Digital testing
- Extremely low offset drift
- Suitable for Rad-Hard environments
Additional key features:
- No missing codes
- Oversampling - reduces requirements for anti-aliasing filter
Sample ADC Implementations
The Digital ADC can be configured for different clock rates, bandwidths and bit resolutions. Some of the possible configurations have been built in FPGAs and their performance is shown in the table below.
|Clock Freq.||Bandwidth||S/(THD+N)||Dynamic Range||Evaluation Board|
|24.578 MHz||10 Hz - 5 kHz||67 dB @ 4 kHz||65 dB @ 1 kHz||Audio Evaluation Board|
|24.578 MHz||10 Hz - 20 kHz||60 dB @ 15 kHz||62 dB @ 2 kHz||Audio Evaluation Board|
Note that ASIC implementations can achieve better results by optimizing the I/O design.
The implementations that are available on evaluation boards are indicated by the name of the evaluation board in the last column of the table. The evaluation boards are described in the following section.
Stellamar has evaluation boards available to enable customers to evaluate the performance of the Digital ADC.
Audio Evaluation Board
The FPGA based audio evaluation board can be configured to demonstrate each of the following versions of the Digital ADC in audio applications:
- ADC 0 - 24.578 MHz clock, 11 bit resolution, 5 kHz bandwidth
- ADC 1 - 24.578 MHz clock, 10 bit resolution, 20 kHz bandwidth
- Analog output through an RCA jack
- SPDIF output through an RCA jack
- I2S output through a 4 pin header
- Parallel data output through a 18 pin header
For ordering information please see the Sales page.
Please see the Digital ADC Factsheet