Stellamar - Digital solutions for an analog world

Digital ADC

Our new Digital ADC technology can be implemented in a digital only silicon technology without using any of the analog IP blocks traditionally used for ADC designs. This reduces the design cycle time and cost of integrating ADCs in to ASICs, and can be implemented in fully digital microchips such as FPGAs avoiding the use of external costly ADCs and saving board space.

Configurations are available that support up to 14 bits of resolution at 10 kHz bandwidth, 12 bits up to 40 kHz bandwidth, and 10 bits up to 100 kHz bandwidth. Development is continuing to support higher bandwidths.

Digital ADC Block Diagram

Block Diagram of the Digital ADC

The analog input is optionally AC-coupled to adjust the DC bias, and then enters the FPGA or ASIC on the non-inverting input of an LVDS input buffer, where it is compared to the reconstructed feedback signal on the inverting input. The difference signal is processed by the digital logic to generate the feedback signal and the ADC output samples that can be used by the rest of the FPGA or ASIC.

The only other signal required by the Digital ADC is a clock input. The frequency of the clock and the characteristics of the tracking loop affect the bandwidth and signal-to-noise ratio of the Digital ADC.

Audio Evaluation Board

Audio Evaluation Board The FPGA based audio evaluation board can be configured to demonstrate each of the following versions of the Digital ADC in audio applications:

  • ADC 0 - 24.578 MHz clock, 11 bit resolution, 5 kHz bandwidth
  • ADC 1 - 24.578 MHz clock, 10 bit resolution, 20 kHz bandwidth
The audio signal is input to the board through an RCA jack. The digitized output can be monitored through 4 different output interfaces to suit various evaluation and test environments:
  • Analog output through an RCA jack
  • SPDIF output through an RCA jack
  • I2S output through a 4 pin header
  • Parallel data output through a 18 pin header
Detailed information is provided in the Audio EVB User Guide

For ordering information please see the Sales page.

ADC Documentation

Please see the Digital ADC Factsheet

Digital Sigma-Delta DAC Family

Stellamar offers a family of Sigma-Delta DACs. These digital DACs can be implemented in digital only silicon technologies such as FPGAs or Digital ASICs.

Within this family, a DAC can be quickly built and customized for your application.

Current performance:

  • Up to 16 bit resolution
  • Up to 100 kHz bandwidth

Digital Controllers for Switch-Mode DC-DC Converters

Stellamar offers fully digital synthesizable controllers that can be easily embedded in digital ASICs or FPGAs. No traditional ADC is required to digitize the output voltage for the feedback loop. Controllers are available for buck (step down), boost (step up) and inverting buck-boost converters.

Buck DC-DC Converter Block Diagram

Block Diagram of the Buck DC-DC Converter

Boost DC-DC Converter Block Diagram

Block Diagram of the Boost DC-DC Converter


Please see the Digital Controllers for DC-DC Converters Application Note

For more product information please email or contact us.

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